DISPS-L2: Efficient Implementation for Communications |
Session Type: Lecture |
Time: Friday, March 19, 13:30 - 15:30 |
Location: Room A1 |
Session Chair: Mohammad Mansour, American University of Beirut, Beirut, Lebanon |
DISPS-L2.1: HARDWARE IMPLEMENTATION OF TRIPLY SELECTIVE RAYLEIGH FADING CHANNEL SIMULATORS |
Fei Ren; Missouri University of Science and Technology |
Yahong Rosa Zheng; Missouri University of Science and Technology |
DISPS-L2.2: EFFICIENT ARCHITECTURE FOR GENERALIZED MINIMUM-DISTANCE DECODER OF REED-SOLOMON CODES |
Jiangli Zhu; Case Western Reserve University |
Xinmiao Zhang; Case Western Reserve University |
DISPS-L2.3: PARTIAL-PARALLEL DECODER ARCHITECTURE FOR QUASI-CYCLIC NON-BINARY LDPC CODES |
Xinmiao Zhang; Case Western Reserve University |
Fang Cai; Case Western Reserve University |
DISPS-L2.4: FPGA-BASED DESIGN AND IMPLEMENTATION OF THE 3GPP-LTE PHYSICAL LAYER USING PARAMETERIZED SYNCHRONOUS DATAFLOW TECHNIQUES |
Hojin Kee; University of Maryland, College Park |
Ian Wong; National Instruments Corp. |
Yong Rao; National Instruments Corp. |
Shuvra Bhattacharyya; University of Maryland, College Park |
DISPS-L2.5: OPTIMIZATION OF MULTISINE EXCITATIONS FOR RECEIVER UNDERSAMPLING |
Michael Schmitz; North Dakota State University |
Roger Green; North Dakota State University |
DISPS-L2.6: DESIGN OF SPARSE FILTERS FOR CHANNEL SHORTENING |
Aditya Chopra; University of Texas at Austin |
Brian Evans; University of Texas at Austin |