My ICASSP 2010 Schedule
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Paper Detail
Paper: | DISPS-L2.4 |
Session: | Efficient Implementation for Communications |
Session Time: | Friday, March 19, 13:30 - 15:30 |
Presentation Time: | Friday, March 19, 14:30 - 14:50 |
Presentation: |
Lecture
|
Topic: |
Design and Implementation of Signal Processing Systems: Programmable and reconfigurable DSP architectures |
Paper Title: |
FPGA-BASED DESIGN AND IMPLEMENTATION OF THE 3GPP-LTE PHYSICAL LAYER USING PARAMETERIZED SYNCHRONOUS DATAFLOW TECHNIQUES |
Authors: |
Hojin Kee; University of Maryland, College Park | | |
| Ian Wong; National Instruments Corp. | | |
| Yong Rao; National Instruments Corp. | | |
| Shuvra Bhattacharyya; University of Maryland, College Park | | |